The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that increases the efficiency of a redundancy circuit for repairing a defective unit cell and reduces a total area, and a method of repairing a defective unit cell in a semiconductor memory device.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into memory cells selected by addresses.
As the operating speed of the system increases and semiconductor integrated circuit technologies advance, semiconductor memory devices are required to input and output data at higher speed. Recently, there has been an ongoing demand for semiconductor memory devices that can store much more data, read and write data more rapidly, and reduce power consumption as well. Furthermore, in line with the development of semiconductor memory fabrication technology, the width of a line for transferring various kinds of signals in a semiconductor memory device, and the size of a unit cell for storing data has become smaller and smaller. As a result, numbers of signal lines and unit cells included in one semiconductor chip are increasing rapidly with the increasing demands for high capacity semiconductor memory.
For this reason, the design and fabrication process of a semiconductor memory device have become more complicated. As each element included in a semiconductor memory device shrinks in size, defects tend to easily occur and particularly, many defects exist between a variety of signal lines or between a signal line and a unit cell. This causes a total defect ratio of the semiconductor memory device to increase. If such defects are not repaired in the semiconductor memory device, production yields may drop. To repair defective unit cells, therefore, the semiconductor memory device generally includes a redundancy circuit configured to detect and repair defects.
The redundancy circuit, which can replace defective unit cells, generally is included in each of a plurality of banks in a semiconductor memory device. Each of the banks includes a cell matrix provided with many unit cells, a row control region where circuits for accessing row addresses are provided, and a column control region where circuits for accessing column addresses are provided. The redundancy circuit includes a row redundancy circuit configured to repair a row address of a defective unit cell, and a column redundancy circuit configured to repair a column address of the defective unit cell. The row redundancy circuit and the column redundancy circuit are respectively included in the row control region and the column control region in each bank.
Meanwhile, a semiconductor memory device becomes more highly integrated, and endeavors are being made to reduce a total area of the semiconductor memory device for improving productivity. In practice, as a semiconductor memory device decreases in area, it is possible to produce a greater number of semiconductor memory devices using one wafer, which improves productivity and reduces fabrication cost. However, as the storage capacity of a semiconductor memory device becomes larger, and thus the number of unit cells also increases, resulting in an increase in the size of a redundancy circuit for replacing a defective unit cell. This makes it difficult to reduce the total area of a semiconductor memory device after all.